Nam Hyun-woo has worked as a staff writer at The Korea Times since 2013, mostly covering business and politics. He currently belongs to the Business Desk where he covers topics such as emerging tech, AI, ICT and Korea's chaebol community. Prior to joining the team, he was the paper's correspondent for the presidential office of Korea during the Yoon Suk Yeol and Moon Jae-in administrations.
Samsung introduces zHBM to stack memory vertically on logic chip
A mockup of Samsung Electronics' zHBM is displayed at its booth for the Future of Memory and Storage 2026 in California, Tuesday (local time). Courtesy of Samsung Electronics
By Nam Hyun-woo
Samsung Electronics showcased its next-generation 3D memory architectures at the Future of Memory and Storage 2026 in California on Tuesday (local time), unveiling mockups of zHBM and zNAND-O.
Samsung outlined its vision for 3D architectures for future memory solutions during a keynote speech by its memory business executives and exhibited mockups of the two new structures at its booth.
ZHBM is an architecture aimed at improving the data processing speed of artificial intelligence (AI) accelerators by shortening the physical distance between logic processors — central processing units, graphics processing units and others — and high-bandwidth memory (HBM).
While conventional HBM is placed beside logic chips, zHBM is stacked directly on top of the processor. By shortening the distance that data must travel, the new architecture delivers higher bandwidth and improved power efficiency.
To support this architecture, Samsung applied hybrid copper bonding, multiwafer bonding and other advanced technologies, which together increase signal transfer speed while reducing thermal resistance.
An infographic introducing zHBM architecture / Courtesy of Samsung Electronics
Samsung said an AI accelerator using zHBM can deliver up to eight times the performance of one equipped with HBM5. The shorter distance between the processor and memory also improves power efficiency by up to threefold compared with HBM5 and reduces thermal resistance by more than half.
Given that major memory makers are currently mass-producing HBM4 and conducting sample tests of next-generation HBM4E, zHBM represents a longer-term architecture envisioned for memory solutions beyond the current HBM roadmap.
ZHBM also supports customer-specific designs, enabling customized intellectual property blocks to be integrated into the interlayer between the memory and AI accelerator to expand memory capacity and enhance accelerator performance.
Samsung Electronics Executive Vice President and Head of Flash Product Lee Jin-yub delivers a keynote speech at the Future of Memory and Storage 2026 in California, Tuesday (local time). Courtesy of Samsung Electronics
The company also introduced zNAND-O, a next-generation high-performance NAND architecture built on its V-NAND technology and available in four- and eight-layer versions. By combining high space efficiency, improved performance and low latency, zNAND-O is optimized for edge AI environments supporting real-time, data-intensive AI applications.
Also at the exhibition, the company unveiled V10 BV-NAND, featuring its new Bonding V-NAND architecture. With more than 400 layers, the new product delivers higher performance and power efficiency while significantly increasing storage density.