Sejong University professor to co-organize int'l workshop on AI chip technologies in Athens

Park Gi-ho, a professor in the Department of Computer Sciences and Engineering at Sejong University, will co-organize the Eighth International Workshop on Domain Specific System Architecture in Athens, Greece, Sunday.

The university said the workshop is part of the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026), which is scheduled to run from Oct. 31 to Nov. 4 in Athens.

The workshop aims to share the latest research advances in artificial intelligence (AI) semiconductors and domain-specific system architecture and promote research collaboration among experts from academia and industry worldwide.

Key topics will include systematic design methodologies for AI accelerators, programming environments for next-generation neural processing units and memory technologies for robotic foundation models.

The workshop is co-organized by Park, professor Sim Jae-woong of Seoul National University and professor Kim Hye-soon of the Georgia Institute of Technology.

The International Symposium on Microarchitecture is a conference with a 59-year history in computer systems and processor architecture design.

Experts from the Massachusetts Institute of Technology (MIT), Nvidia, Korean AI chipmaker FuriosaAI and the Institute of Science Tokyo will deliver invited talks at the workshop.

MIT professor Joel Emer, who also serves as a senior distinguished research scientist at Nvidia, will discuss a systematic approach to AI accelerator design that takes into account the characteristics of AI models.

He will explain how linking AI models’ computational characteristics with hardware architectures can help improve accelerator efficiency.

Kang Jee-hoon, chief research officer at FuriosaAI, will discuss the programming environment for the company’s latest AI accelerator, the RNGD neural processing unit (NPU).

His talk will cover software development tools, including compilers, as well as techniques for making effective use of AI accelerators.

Professor Daichi Fujiki of the Institute of Science Tokyo will discuss memory mechanisms in AI models.

He will introduce techniques for generating certain AI model parameters during hardware execution, as well as approaches to data storage and generation.

Researchers from the Universitat Politècnica de Catalunya in Spain and the University of Texas at San Antonio will present their findings during the technical paper sessions.

Topics will include scheduling techniques for efficiently processing graphics workloads and methods that leverage cache locality to accelerate graph neural network computations on graphics processing units (GPUs).