Samsung showcases chip 3D architecture strategy at SEMICON Taiwan

Samsung Electronics on Tuesday showcased its 3D architecture strategy to break through current limitations in memory chip manufacturing during SEMICON Taiwan 2026, an international exhibition covering semiconductor design, manufacturing, testing and packaging.

According to the company, Samsung Electronics Device Solutions Vice President Choi Jang-seok delivered a keynote speech at the Memory Executive Summit, a preview event for SEMICON Taiwan 2026, which will begin its three-day run on Wednesday.

During his speech, Choi said Samsung is pushing the limits of memory technology with its “CUBE” strategy, which applies 3D technologies across memory chip manufacturing processes to improve capacity, utilization, bandwidth and efficiency.

In memory chips, 3D architecture stacks chip dies or other components vertically to shorten the physical distance data must travel, increase data pathways and improve energy efficiency.

It is called 3D architecture because chips or memory dies are stacked vertically instead of being placed side by side on a two-dimensional plane. High-bandwidth memory (HBM), widely used in artificial intelligence (AI) accelerators, is an example of 3D architecture.

“We are no longer constrained by the size of the printed circuit board, because memory capacity can be increased by stacking components vertically, without making the board larger,” Choi said.

“By dramatically shortening the distance between dies, we can create vertical data highways and significantly increase bandwidth.”

The vertical highway is through-silicon vias (TSVs), tiny holes that run through each silicon die and are filled with copper. They create direct electrical paths between stacked dies, shortening the data distance from the millimeter scale in conventional memory to just tens of micrometers.

Since thousands of TSVs can be used in a single stack, they also allow more data to move at the same time, helping HBM deliver higher bandwidth with better power efficiency.

“The ultimate goal of 3D architecture is to reduce the energy required to transmit a single bit of data, and Samsung is maximizing performance per watt by improving structural efficiency,” Choi said.

During the event, Samsung introduced its HBM technologies by generation and outlined its road map for next-generation products.

The company is currently developing HBM5, the next generation of HBM4E, which is currently undergoing sample testing at major customers. Samsung said it is targeting HBM5 to deliver twice the performance of HBM4E, a 20 percent improvement in performance per watt and a 20 percent reduction in thermal resistance.

Samsung also said it is preparing zHBM and zNAND-O as future memory technologies.

First unveiled at Future of Memory and Storage 2026 in California last month, zHBM is an architecture that stacks HBM directly on top of logic processors, such as graphics processing units or central processing units.

Samsung said zHBM is being developed with targets of delivering eight times the performance of HBM4E, tripling performance per watt and reducing thermal resistance by 75 percent to 90 percent. The company said zHBM also allows customer-specific intellectual property blocks to be integrated into an interlayer between the memory and AI accelerator.

“The key to 3D is not simply stacking components, but how each layer is utilized. Samsung is optimizing the placement of logic and memory to reduce data processing latency,” Choi said.

ZNAND-O is a 3D-packaged product that stacks four or eight V-NAND dies using TSVs. It is designed to support the massive storage capacity required for advanced AI models while delivering seven times higher read bandwidth and power efficiency than conventional NAND storage. Samsung said zNAND-O’s sampling is scheduled to begin in 2028.